With a remarkably increasing number of data communication services due to, among others, the popularization of the Internet in recent years, an optical transmission system using optical fibers is applied to mainly trunk networks in a wide range of networks up to metro networks. Nowadays, it is time to implement production of a 10-Gbps optical transmission system for trunk networks on a full scale. In addition, development of a communication LSI for a next-generation optical transmission system with a transmission speed of 40 Gps has been started. So far, in an interface of a Framer IC for an optical transmission module, there has been adopted a transmission system for transmitting data and a clock signal in parallel.
Non-patent references 1 and 2 each disclose a typical transmission system. Non-patent reference 1 is a document with a title of “A 20 Gb/s CMOS Multi-Channel Transmitter and Receiver Chip Set for Ultra-High Resolution Digital Display,” 2000 IEEE International Solid-State Circuits Conference TP 15.7. On the other hand, non-patent reference 2 is a document with a title of “5 Gb/s Bidirectional Balanced-Line Link Compliant with Plesiochronous Clocking,” 2001 IEEE International Solid-State Circuits Conference 4.4. The inventors of the present invention have studied conventional technologies disclosed in documents including non-patent reference 1 and pointed out technological problems as a result of the study. By referring to diagrams, the following description sequentially explains the conventional technologies and their problems.
FIG. 16 is a block diagram showing an optical transmission module developed by the inventors and serving as a prerequisite to the present invention. FIG. 17 is a block diagram showing an SFI-5 Rx LSI employed in the optical transmission module shown in FIG. 16.
In a 40 Gbps optical transmission module shown in FIG. 16 as a next-generation optical transmission module employing an SFI-5 Rx LSI shown in FIG. 17, an interface unit processes signals each having a large number of bits and a high frequency. For the large number of bits and the high frequency, there has been proposed interface specifications SFI-5 with a CDR (Clock and Data Recovery) system used as a prerequisite. The CDR system is a system for extracting a clock signal from data. A CDR block employed in the SFI-5 Rx LSI shown in FIG. 17 extracts a clock signal from data and receives the data. A FIFO block absorbs clock skews generated between channels. The function of the FIFO blocks is indispensable to a high-speed I/F LSI.
FIG. 18 is a block diagram showing a typical configuration of a CDR (Clock and Data Recovery) circuit employing a commonly known VCO (Voltage-Controlled Oscillator). The inventors of the present invention developed the CDR circuit. In the CDR circuit, a phase comparator generates UP and DOWN signals as a result of phase comparison. Electric charge representing a difference between the UP and DOWN signals is accumulated in a charge pump 1801. A loop filter 1802 removes high-frequency components from the voltage of a capacitor employed in the charge pump 1801 before the voltage is supplied to an oscillator 1803. Since the loop filter 1802 must employ a capacitor with a large capacitance of the order of 100 pF in this configuration, the configuration has a shortcoming that it is necessary to increase the area of the CDR circuit to about 500 square-microns. Thus, the CDR circuit is not suitable for bit-count enhancement of an optical transmission system.
FIG. 19 is a block diagram showing the configuration of a variable delay type phase generator adopted in a CDR circuit serving as a comparison example assumed by the inventors of the present invention. The figure is given to show problems to be solved by the present invention. The configuration comprises a phase comparator 1903, a counter 1905 and a clock-phase generation unit 1906. The phase comparator 1903 is a component for comparing the phase of input data 1901 with the phases of data recovery clock signals 1902 generated internally. As a result of comparison, the phase comparator 1903 outputs UP and DOWN signals 1904 indicating directions of the change of the clock phase. The counter 1905 is a component for controlling the frequency at which the UP and DOWN signals 1904 are fed back to a means for outputting a clock phase. The clock-phase generation unit 1906 is a component for generating the output phases of the clock signals from a signal output by the counter 1905. The clock-phase generation unit 1906 comprises a phase interpolation control unit 1907 and 2 phase interpolation circuits 1908.
The phase interpolation circuits 1908 are each connected to a load resistor having 2 common left and right differential pairs. If 2 clock signals with phases different from each other by 90 degrees are supplied to the left and right differential pairs respectively, a signal having a mid phase between the 2 phases is output. By controlling a current source of the differential pairs, the mid phase can be generated as a staircase like phase. Let symbols θ and f denote the phases of the signals supplied to the left and right differential pairs and combinations of the phases θ and f be the following 4 combinations, i. e., a combination of 0 degrees and 90 degrees, a combination of 90 degrees and 180 degrees, a combination of 180 degrees and 270 degrees and a combination of 270 degrees and 0 degrees. In this case, by controlling a current generated by the current source to magnitudes I0 to I16, the output phase can be changed to values at 64 (=16 stages×4, where the integer 4 is the number of phase combinations) stages. The 16 stages correspond to the 16 current magnitudes I0 to I16.
FIG. 20 shows a flowchart representing operations carried out by the CDR circuit shown in FIG. 19. First of all, a phase comparator compares data 2001 with the edge of a clock signal 2002 generated internally. If the phase of the clock signal lags behind the phase of the data, the comparator outputs the UP signal 2003. If the phase of the clock signal leads ahead of the phase of the data, on the other hand, the comparator outputs the DOWN signal 2004. A counter counts the number of UP signals 2003 and the number of DOWN 2004. As the number of UP signals 2003 or the number of DOWN 2004 reaches a number N, the counter outputs a signal to the clock generation unit 2005, which generates the aforementioned clock signal 2002 on the basis of the UP and DOWN signals.
FIG. 21 is a diagram showing an outline of operations carried out by the CDR circuit shown in FIG. 19. A time-to-time processing method is adopted as the conventional processing method for reflecting results of the edge detection in the recovered clock signal. A cycle from phase detection to reflection of phase-comparison results in a recovered clock signal is divided into a phase detection period from the phase comparison in the phase comparator to an operation carried out by the counter to output a signal, a clock-phase selection process and a clock delay, which is a delay incurred by the recovered clock signal. In accordance with the time-to-time processing method, before a cycle up to reflection of edge detection results in a recovered clock signal is completed, the next cycle is started in order to reduce a clock control interval. In this way, phases can be detected and results of the phase detection can be fed back with a higher degree of precision.
FIG. 22 shows typical timing charts of operations carried out by the CDR circuit shown in FIG. 19. As a method of further reducing the clock control interval, there is a method in which a dual counter is employed for carrying out process A and process B concurrently. Of course, there is also a method of using a single counter for processing process A only.
The description begins with a state in which clock signal 3 has been selected as an initial recovered clock signal. Since the rising edge of the recovered clock signal leads ahead of the rising edge of the data, in phase detection (1) of process A, the number of DOWN_A pulses is counted. The output of the counter is fed back to phase-selection and clock-outputting processes and, as N DOWN_A pulses are counted, the recovered clock signal is switched to clock signal 2. In addition, process B is being carried out concurrently with process A and, from the same processing as that described above, clock signal 2 is selected. In the continuation of process A, data edges are moving due to a wander, causing the raising edge of the recovered clock signal to lag behind the data edge. For this state, before results of phase detection (1) are reflected, N UP_A pulses are counted during phase detection (3), and the phase-selection and clock-outputting processes switch the recovered clock signal to clock signal 3.
FIG. 23 is a diagram showing basic operations carried out by the CDR circuit shown in FIG. 19. If a rising edge of data exists in edge detection width A between rising edge 2 of recovered clock signal 2 and rising edge 3 of recovered clock signal 3, the clock signal is shifted in the plus direction by a phase differential of T/N. If a rising edge of data exists in edge detection width B between rising edge 2 of recovered clock signal 2 and rising edge 1 of recovered clock signal 1, on the other hand, the clock signal is shifted in the minus direction by a phase differential of T/N. Data is taken in and output on a falling edge of a clock signal.
FIG. 24 is a diagram showing an edge detection method (that is, an edge-tracking method) adopted by the CDR circuit shown in FIG. 19. The following description explains a process to take in data in edge detection for data having jitters. As the jitters, a value of 0.7 UI is taken into consideration. The value of 0.7 UI is a result of adding a jitter increase of 0.025 UI caused by the I/O to a standard value of 0.675 UI. This standard value is an SFI-5 (Serdes Framer Interface Level 5) standard value.
With clock timing 1, the phase of the clock signal is compared with the phase of data by comparing the rising edge of the clock signal with the rising edge of a data pulse far way from an eye. In the case of clock timing 1, the falling edge of the clock signal is shifted to a position outside the eye serving as a data recovery width, existing in the 0.7 UI jitter range. Thus, if the fact that data jitters deviate from D0 to Dn is taken into consideration, at Dn, for example, it is quite within the bounds of possibility that the data preceding Dn by 1 cycle is output. With clock timing 2, on the other hand, the phase of the clock signal is compared with the phase of data by comparing the rising edge of the clock signal with the rising edge of a data pulse close to the eye serving as a data recovery width. Also in the case of clock timing 2, the falling edge of the clock signal is shifted to a position outside the eye serving as a data recovery width, existing in the 0.7 UI jitter range. Thus, if the fact that data jitters deviate from D0 to Dn is taken into consideration, at D0, for example, it is quite within the bounds of possibility that the data succeeding D0 by 1 cycle is output.
FIG. 25 is a diagram showing the definition of a wander, which is a long-period phase deviation. A wander prescribed in the SFI-5 standard is defined as attributes of a sinusoidal signal with a P-P amplitude of 10.65 UI and a period Tw in the range 5.3 to 6.7 micron sec. FIG. 26 is a diagram showing a characteristic representing the dependence of the wander Tb on the phase detection period Ta. For a counter count value of 8 in the conventional CDR circuit, the wander Tb is found to be 5.2 ps for a phase detection period Ta of 8 UI. If the frequency of the signal supplied to the counter is divided, the wander Tb is found to be 10.4 ps for a phase detection period Ta of 16 UI.
FIG. 27 is a diagram showing relations between the eye and clock jitters with a wander generated in the CDR circuit shown in FIG. 19. Prior to generation of a wander, a clock falling edge may exist at a position of several ps up to a jitter range within an eye. Thus, data D0 to Dn can correctly be output. In the case of a wander changing during the conventional detection period, on the other hand, the data edge deviates with a wander Tb of to 10 ps. Thus, the clock falling edge is shifted to a position outside the eye, existing in the 0.7 UI jitter range. As a result, at Dn, for example, it is quite within the bounds of possibility that the data preceding Dn by 1 cycle is output.
In the typical edge detection described above, it is quite within the bounds of possibility that, due to a wander, data taken in at a clock immediately preceding the feedback of the edge detection may be data succeeding the supposed data by 1 cycle. In addition, since a wander reduces the width of data recovery, it is necessary to decrease Tb (wander/phase detection period).
FIG. 28 is a diagram showing a relation between the data edge and the edge detection width with a wander generated in the CDR circuit shown in FIG. 19. In the conventional CDR circuit, after N results of phase comparison are counted, a recovered clock signal is generated. While a data edge at the first edge detection exists in the edge detection width, at the Nth edge detection shown in the figure, the data edge is shifted to a position outside the edge detection width due to a wander Tb. Thus, since a result of phase comparison cannot be output, N results of phase comparison cannot be counted so that neither a recovered clock signal is generated nor the phase changes.
As described above, in this typical edge detection, the phase of data with an edge supposed to be in edge detection width A deviates by a quantity Tb during a phase detection period due to a wander so that the edge is shifted to a position outside the edge detection width. Thus, results of phase comparison cannot be counted and the phase does not change. It is therefore feared that the clock edge does not follow the data edge. In addition, data may not be taken in correctly in dependence on the quantity Tb of the wander. It is thus quite within the bounds of possibility that data succeeding the supposed data by 1 cycle is output.
As described above in detail, the conventional clock data recovery circuit has the following problems:
(1) The configuration of the conventional clock data recovery circuit does not include sufficient consideration of an edge detection method for data with a jitter width exceeding 0.5 UI. That is to say, let data with a jitter width exceeding 0.5 UI be handled by adoption of an edge detection technique based on an edge-tracking method. In this case, if the phase of a data edge on the eye side is compared with the phase of a clock rising edge, an edge for recovery of data on the clock falling edge is shifted out from the data recovery width. As a result, the data cannot be recovered correctly. In other words, the edge-tracking method can correctly recovery only data with a jitter width of about 0.5 UI or below.
As is obvious from the above description, the clock data recovery circuit described above has a problem of a poor jitter-tolerance characteristic.
(2) The configuration of the conventional clock data recovery circuit does not include sufficient consideration of an edge detection method for correctly recovering data even in the event of a wander. That is to say, since a clock falling edge may exist at a position of several ps up to a jitter range within the eye prior to generation of a wander, if a wander is generated in the jitter direction, the clock falling edge will be shifted to a position in the jitter range so that data cannot be recovered.
As is obvious from the above description, the clock data recovery circuit described above has a problem of a narrow data recoverability range with a wander taken into consideration.
(3) The configuration of the conventional clock data recovery circuit does not include sufficient consideration of an edge detection method for placing a data edge in an edge detection width even in the event of a wander. That is to say, at the first edge detection in a phase detection period, a data edge may exist at a position on the inner side several ps from the edge of the edge detection width. At the Nth edge detection, since the data edge deviates due to a wander Tb, it is quite within the bounds of possibility that the data edge is shifted to a position outside the edge detection width. In other words, since results of phase comparison cannot be output, N results cannot be counted so that neither a recovered clock signal is generated nor the phase is changed.
As is obvious from the above description, the clock data recovery circuit described above has a problem that the clock signal has a poor tracking characteristic in the event of a wander.
(4) The configuration of the conventional clock data recovery circuit does not include sufficient consideration of reduction of power consumption by the phase interpolation circuit. That is to say, the current of the phase interpolation circuit is controlled to magnitudes separated away at intervals each equal to a current pitch of I1 mA. To put it concretely, the magnitudes of the currents I0 to I16 are set as follows: I0=0 mA, I1=the magnitude of a circuit operation limit current [mA] and I16=I1×16 mA. That is to say, the phase selection causes a current always having a magnitude equal to 16 times the circuit operation limit current to flow.
As is obvious from the above description, the clock data recovery circuit described above has a problem of large power consumption.
It is thus a first object of the present invention addressing the problem described in section (1) to provide a clock data recovery circuit having an improved jitter tolerance characteristic.
It is thus a second object of the present invention addressing the problem described in section (2) to provide a clock data recovery circuit having a broadened data recoverability range to cope with a wander generated in the clock data recovery circuit.
It is thus a third object of the present invention addressing the problem described in section (3) to provide a clock data recovery circuit having an improved tracking characteristic to cope with a wander generated in the clock data recovery circuit.
It is thus a fourth object of the present invention addressing the problem described in section (4) to provide a clock data recovery circuit having a reduced power consumption.